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CY62138V MoBLTM
2-Mbit (256K x 8) Static RAM
Features
* High Speed: -- 70 ns * Low voltage range: -- 2.7V - 3.6V * Ultra-low active power * Low standby power * Easy memory expansion with CS1/CS2 and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power * Available in non Pb-free 36-ball FBGA package This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that reduces power consumption by 99% when addresses are not toggling. The device can be put into standby mode when deselected (CS1 HIGH or CS2 LOW). Writing to the device is accomplished by taking Chip Enable One (CS1) and Write Enable (WE) inputs LOW and Chip Enable Two (CS2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable One (CS1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CS2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CS1 HIGH or CS2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CS1 LOW, CS2 HIGH, and WE LOW). The CY62138V is available in a 36-ball FBGA package.
Functional Description
The CY62138V is a high-performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra-low active current.
Logic Block Diagram
Pin Configuration
36-ball FBGA TOP View
1 A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9 OE A10 NC CS1 A11 A17 A16 A12 A15 A13 2 A1 A2 3 CS2 WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 VCC VSS I/O2 I/O3 A14 A B C D E F G H
Data in Drivers
I/O0 I/O1
ROW DECODER
A4
A5
SENSE AMPS
A0 A1 A2 A3 A6 A7 A8
I/O2 I/O3 I/O4 I/O5
256K x 8 ARRAY
CS 2
CS1 WE OE
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Cypress Semiconductor Corporation Document #: 38-05088 Rev. *B
A9 A 10 A 11 A12 A13 A14 A15 A16 A17
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised July 21, 2006
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CY62138V MoBLTM
Product Portfolio
Power Dissipation (Industrial) VCC Range (V) Product CY62138V VCC(min) 2.7 VCC(typ)[1] 3.0 VCC(max) 3.6 Speed (ns) 70 Operating, ICC (mA) Typ.[1] 7 Maximum 15 1 Standby, ISB2 (A) Typ.[1] Maximum 15
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................-65C to +150C Ambient Temperature with Power Applied ..................................................-55C to +125C Supply Voltage to Ground Potential..................-0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ........................................ -0.5V to VCC + 0.5V
DC Input Voltage[2] .................................... -0.5V to VCC + 0.5V Output Current into Outputs (LOW) .............................20 mA Static Discharge Voltage .......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Device CY62138V Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.6V
Electrical Characteristics Over the Operating Range
CY62138V Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled IOUT = 0 mA, f = fMax = 1/tRC, CMOS Levels IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-down Current-- CMOS Inputs Automatic CE Power-down Current-- CMOS Inputs CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = fMax CE > VCC-0.3V VIN > VCC-0.3V or VIN < 0.3V, f = 0 VCC = 3.6V 1 VCC = 3.6V Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V VCC = 3.6V VCC = 2.7V 2.2 -0.5 -1 -1 +1 +1 7 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 Typ.[1] Max. Unit V V V V A A mA
1
2
mA
100
A
ISB2
15
A
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 6 8 Unit pF pF
Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25C. 2. VIL(min) = -2.0V for pulse durations less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05088 Rev. *B
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CY62138V MoBLTM
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 VCC Typ 10% GND < 5 ns ALL INPUT PULSES 90% 90% 10% < 5 ns
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters R1 R2 RTH VTH
3.0V 1105 1550 645 1.75
Unit Ohms Ohms Ohms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = 1.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, No input may exceed VCC+0.3V 0 100 Conditions[4] Min. 1.0 0.1 Typ.[1] Max. 3.6 5 Unit V A
tCDR[3] tR
Chip Deselect to Data Retention Time Operation Recovery Time
ns s
Data Retention Waveform[5]
DATA RETENTION MODE VCC
VCC(min.)
tCDR
VDR > 1.0V
VCC(min.)
tR
CE
Notes: 4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 5. CE is the combination of both CS1 and CS2.
Document #: 38-05088 Rev. *B
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CY62138V MoBLTM
Switching Characteristics Over the Operating Range[4]
70 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[8, 9] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[6, 7] WE HIGH to Low-Z[6] 10 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[6] OE HIGH to High-Z[6, 7] CE LOW to Low-Z[6] CE HIGH to High-Z[6, 7] CE LOW to Power-up CE HIGH to Power-down 0 70 10 25 5 25 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes: 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle.
Document #: 38-05088 Rev. *B
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CY62138V MoBLTM
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[5, 11, 12]
tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% tPD ICC 50% ISB tHZOE tHZCE DATA VALID
HIGH IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)[5, 8, 13, 14]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O
NOTE 15
tHD
DATAIN VALID tHZOE
Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05088 Rev. *B
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CY62138V MoBLTM
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[5, 8, 13, 14]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATA VALID IN tHD tHA tSCE
Write Cycle No. 3 (WE Controlled, OE LOW)[5, 9, 14]
tWC ADDRESS
CE tAW tSA WE tSD DATA I/O tHD tHA
NOTE 15
tHZWE
DATA VALID IN tLZWE
Document #: 38-05088 Rev. *B
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CY62138V MoBLTM
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2
CC
STANDBY CURRENT vs. AMBIENT TEMPERATURE 3.0 2.5 VCC = VCC typ. VIN = VCC typ.
1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7
NORMALIZED I
ISB2 A
I CC VIN = VCC typ. TA = 25C
2.0 1.5 1.0 0.5 0.0 -0.5 3.2 3.7
ISB
-55
25
105
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (C)
NORMALIZED STANDBY CURRENT vs. SUPPLY VOLTAGE 1.4 ISB2 1.0 0.8 0.6 0.4 0.2 0.0 1.0 VIN = VCC typ. TA = 25C NORMALIZEDICC 1.2 NORMALIZED ISB
NORMALIZED I CC vs.CYCLE TIME 1.50 VCC = 3.3V TA = 25C
1.00
0.50
0.10 1.9 2.8 3.7
1
5
10
15
CYCLE FREQUENCY (MHz) SUPPLY VOLTAGE (V)
Truth Table
CS1 H X L L L CS2 X L H H H WE X X H L H OE X X L X H Inputs/Outputs High-Z High-Z Data Out Data In High-Z Mode Deselect/Power-down Deselect/Power-down Read Write Deselect, Output Disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 70 Ordering Code CY62138VLL-70BAI Package Diagram 51-85099 Package Type 36-ball Fine Pitch Ball Grid Array (7 x 7 x 1.2 mm) Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05088 Rev. *B
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CY62138V MoBLTM
Package Diagram
36-ball FBGA (7 x 7 x 1.2 mm) (51-85099)
TOP VIEW
BOTTOM VIEW O0.05 M C A1 CORNER
A1 CORNER
O0.25 M C A B O0.300.05(48X)
12 A B C 7.000.10
3
4
5
6
6
5
4
3
2
1 A B C
7.000.10
E F G H
5.25
D
0.75
D E 2.625 F G H
A
A
1.875 0.75
B
7.000.10 B
3.75 7.000.10
0.530.05
0.15(4X) 0.210.05 0.15 C
51-85099-*C
0.25 C
SEATING PLANE 0.36 C
1.20 MAX.
More Battery Life is a trademark, and MoBL is a registered trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05088 Rev. *B
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62138V MoBLTM
Document History Page
Document Title: CY62138V MoBLTM 2-Mbit (256K x 8) Static RAM Document Number: 38-05088 REV. ** *A *B ECN NO. 107348 114936 486789 Issue Date 06/12/01 05/28/02 SEE ECN Orig. of Change SZV CBD VKN Description of Change Change from Spec #: 38-00729 to 38-05088 Replaced wrong package diagram with correct diagram (36-ball FBGA [see p. 8]) Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court". Updated Ordering Information table
Document #: 38-05088 Rev. *B
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